The next generation of electrical/electronic (E/E) architecture for software-defined vehicles (SDV) is evolving toward centralization. By 2032, McKinsey analysis estimates that 30 percent of all vehicles produced globally will have E/E architectures with zonal controllers (Exhibit 1). Importantly for the semiconductor industry, this shift will require centralized, high-performance compute units. In the next ten years, the market for automotive microcomponent and logic semiconductors is expected to grow to $60 billion in 2032. The overall automotive semiconductor market is expected to increase from $60 billion to $140 billion over the same timeframe. Its CAGR of 10 percent exceeds all other verticals for the semiconductor market.
The centralized, high-performance compute units usually provide the functionality for advanced driver assistance systems (ADAS) or, in the future, automated driving (AD), as well as infotainment and vehicle motion tasks. Two archetypes—separate, domain-specific compute units and cross-domain, central compute units—will dominate the upcoming generation of E/E architecture (Exhibit 2). By nature of this, OEMs and tier-one suppliers can realize centralized compute units in different ways, such as via rack-based setups, a printed circuit board (PCB) with multiple chips, or a fusion chip for multiple domains.
In all cases, choosing the most efficient underlying system-on-chip (SoC) or system-in-package (SiP) is crucial for several reasons. First, SoCs and SiPs realize the essential computations necessary to drive cars autonomously (for example, by implementing the perception function that recognizes other vehicles and traffic participants), in addition to providing cutting-edge infotainment services and enabling generative AI (gen AI) use cases (for example, for in-car assistants). Second, SoCs and SiPs are a big driver of cost, and they greatly affect the overall bill of materials (BOM). Last, their power consumption may play a role in ensuring energy-efficient operations of the vehicle, which is particularly relevant for the transition to battery electric vehicles (BEVs).
Automotive OEMs are therefore highly invested in the continuous improvement of compute power and efficiency. As a result, two emerging trends within the ADAS/AD and infotainment domains have gained traction in the concept phase of upcoming E/E architectures: fusion chips and chiplet-based chip designs.
This article will discuss fusion chips and chiplet-based chip designs as enablers for centralized computing in future E/E architectures and discuss why they constitute an important element for chief technology officers as they make strategic decisions regarding centralized computing.
Advancing centralized computing in ADAS/AD and infotainment through fusion chips
Fusion chips may be seen as the logical next step to increase the consolidation and integration of SDV functionalities and computations. Namely, fusion chips merge the functionalities of infotainment and ADAS/AD onto one piece of silicon, resulting in a single “fusion” chip.
At first glance, the technical requirements of this consolidation seem to make sense. Today, both ADAS/AD and infotainment domains require state-of-the-art multi-core central processing units (CPUs), graphics processing units (GPUs), AI accelerators, and digital signal processors, and both domains aim for implementation at very small node sizes (that is, less than ten nanometers) to increase compute power and power efficiency. At the same time, several aspects of this consolidation reveal how different both domains are:
- While the infotainment domain has some applications relevant to functional safety (for example, to support the cockpit cluster), the need for automotive safety integrity level B (ASIL-B) and ASIL-D functional safety compliance is much more pronounced in the ADAS/AD domain, which has to carry out many real-time critical functionalities (for example, actuator control tasks). Pure safety island–based approaches may not be enough here, as are commonly pursued for infotainment.
- The need for close hardware/software (HW/SW) co-design is particularly pronounced in the ADAS/AD domain to optimize the compute hardware (for example, AI accelerators) for the specific neural network architectures (for example, convolutional neural networks and transformers) that implement the perception element.
In the past two years, despite several challenges associated with fusion chip design, fabless semiconductor players and new entrants have made this theoretical idea a reality.1 Furthermore, several tier-one suppliers have presented compute unit designs using fusion chips, advocating for their benefits in the context of an SDV.
Benefits of fusion chips for automotive OEMs
By using fusion chips, OEMs could reduce the overall number of physical compute units and further simplify the overall integration and consolidation of compute logic. For example, this approach is relevant for facilitating over-the-air (OTA) updates during the entire vehicle life cycle—a key enabler for SDVs. Additionally, OEMs could simplify tool chains and development frameworks across the infotainment and ADAS/AD domains, with expected cost advantages in the long run.
This year, in collaboration with the Global Semiconductor Alliance (GSA), McKinsey surveyed stakeholders from the entire automotive semiconductor value chain. Participants stated that facilitated development paradigms (such as development environments and tool chains) and cost reasons (such as savings in intellectual property and packaging) would be the top factors (28 percent and 57 percent, respectively) in their decision to adopt fusion chips that combine ADAS/AD and infotainment functions.
Resolving challenges of fusion chips for automotive OEMs
At the same time, the transition to fusion chips will also entail some challenges. First, fusion chips require higher technical complexity (for example, validation efforts) to guarantee freedom from interference; this is because infotainment and ADAS/AD must be separated, and any compute requirements from one domain may not interfere with the other. Furthermore, there will be increased organizational burden in terms of alignment needs between infotainment and ADAS domains.
Second are issues complying with the redundancy requirements for Level 3 (L3) and above autonomous driving systems.2 Level 3 systems require conditionally autonomous driving, redundancy on compute, actuators (braking and steering), and a power supply. When the compute functionality for infotainment and ADAS/AD are combined onto a single, highly integrated chip, deploying a second chip may not be necessary because the infotainment domain would not need additional compute power in the case of primary chip failure. In this case, deploying a second chip could create overhead.
Additional challenges lie with more-complex conformity requirements for electromagnetic compatibility (EMC) because of the associated functional safety requirements; the limited possibility for individual optimizations, such as for functional safety requirements and dedicated accelerators; and the loss of ability to choose the best supplier for both domains and higher lock-in effect.
In the survey, participants also identified the top three challenges for adopting fusion SoCs as ensuring freedom of interference (33 percent), dealing with organizational reasons3 (25 percent), and addressing redundancy requirements for ADAS/AD (19 percent). Scalability in terms of compute power and physical and manufacturing difficulties (13 percent and 10 percent) were perceived as less of a challenge.
Expected timeline and rollout for fusion chips
Given the redundancy requirements for higher levels of autonomy, fusion chips may be an especially viable solution for deployment scenarios targeting L0 to L2 applications (for example, adaptive cruise control [ACC], lane departure warning [LDW], and automated emergency braking [AEB]) rather than scenarios targeting L3 applications and above (for example, hands-off and eyes-off scenarios), especially before 2030. Moreover, fusion SoCs may take over functionalities that lie between the two domains, such as driver monitoring and occupant detection—areas that are gaining importance in light of the upcoming New Car Assessment Program (NCAP) regulations in Europe.4
On the infotainment side, fusion chips are well suited to assume control over a broad range of functionalities, such as the cockpit cluster, center stack and passenger displays, augmented reality display, surround-view parking, rear-seat entertainment, and e-mirrors.
Based on recent public announcements,5 first deployments of fusion chips targeting series vehicles can be expected from 2026 to 2027, with uptake dominated by volume OEMs that are focused on cost efficiencies and disruptors that have a limited technical legacy and are more open to technical innovations.
Employing chiplets for automotive tailored chip designs
In broader terms, “chiplets” refer to a form of advanced packaging6—that is, innovative techniques and technologies used to enhance the performance, functionality, and integration of semiconductor devices beyond the traditional packaging methods. A chiplet architecture represents a paradigm shift in semiconductor design, enabling the modular integration of multiple specialized chips into one package. Chiplets allow OEMs to choose the optimal technological solution for each subcomponent, highlighting that not all components need to be manufactured on cutting-edge node sizes. Thus, using chiplet-based designs is possible in dedicated ADAS/AD and infotainment chips and fusion chips alike.
As a result of the enabled flexibility, one may even consider use cases of chiplets in scenarios where the overall chip is designed to support different compute loads (for example, by using dedicated CPU chiplets). As such, zonal controllers might also constitute an interesting application area, given that their compute requirements vary depending on the archetype (for example, simple input/output aggregators versus full-fledged compute units).
Instead of having all the functionalities of a modern chip (for example, CPU, memory, AI accelerators, serializers, and deserializers) on a single piece of silicon, the individual components of a chiplet are implemented separately using the technology node size best suited and most economically viable for the application (Exhibit 3). That means the CPU and accelerator subsystems may resort to the smallest node sizes available, while other functionalities may be implemented on larger node sizes. To ensure that the individually manufactured components still work together, a common interface standard such as the Universal Chiplet Interconnect Express (UCIe) is needed. As discussed later, many efforts to create these standards are under way.
The benefits of chiplet-based chip designs for automotive OEMs
In the automotive context, experts reference two benefits of chiplet-based chip designs most often:
Overall die size reduction. Using chiplets avoids the increasing die sizes (area) of a monolithic design approach. In the past five years, the die areas of sophisticated chips have increased in size, almost reaching the reticle limit of extreme ultraviolet lithography, at 858 square millimeters.7 This issue became prominent for GPUs used in data centers because the larger die size allowed for more transistors, which could enhance computational power and processing capabilities. Keeping in mind that the yield of a process is limited by the defect density (number of defects per unit area), larger dies are more likely to encompass one or more defects simply because they cover more area. Even a single defect can render a die nonfunctional. Higher yields resulting from smaller die sizes would lead to lower costs in the long run.
While this effect is an important benefit of chiplets, automotive chips are not expected to reach such sizes before the mid 2030s. Instead, for the automotive vertical, the Lego principle is more important.
Lego principle. The Lego principle—or modular chip design enabled by standards—allows automotive OEMs to mix and match components from a pool or library of existing designs tailored to their specific needs. The benefits of this principle include the ability to reuse components. Because the automotive sector manufactures at lower volumes than other market segments (for example, yearly vehicle volumes of nearly 100 million versus smartphone shipments of nearly 1.5 billion per year), tailored reuse of components would improve the cost efficiency of targeted chip designs. Other benefits include an accelerated time to market for new chips, improved scalability by selecting the components that are really needed, and more supplier options for specialized chips such as accelerators.
By a significant margin (61 percent), survey respondents across the automotive semiconductor value chain cited the flexibility to design the best chip through a mix-and-match or Lego principle as the main motivation for adopting chiplets in the industry. Reducing the total cost of operation and achieving higher volumes for individual IP components were seen as important benefits of chiplet-based designs but were less impactful (19 percent).
The chiplet ecosystem as a critical enabler
Ecosystems are crucial to the success of chiplets. These ecosystems promote standardization and foster the environments that encourage chiplet adoption across different industry verticals (for example, data centers and automotive).
The UCIe standard is among the most important advances in standardization. Since publication of the first standard (UCIe 1.0) in March 2022, an automotive working group was formed that made automotive-tailored contributions to revisions of the standard.8
Apart from standardization, emerging ecosystems have a role in facilitating their adoption. For example, the Automotive Chiplet Alliance sponsored by Imec, an independent nanoelectronics R&D hub, gathered more than 50 automotive semiconductor value chain participants to discuss and exchange ideas about the progress of automotive chiplet designs.9
The challenges of chiplet-based chip design for automotive OEMs
Chiplet technology is still young. OEMs must consider the challenges of using chiplets, especially when thinking about a series deployment.
Automotive readiness. For automotive readiness, chiplet designs must fulfill all required device and manufacturing specifications (such as AEC-Q100 and IATF 16949) and withstand harsh environments, including vibration and temperature. Current use cases in data centers provide more stable environments and fewer challenges than those encountered in automotive manufacturing.
Interconnect standardization. As previously discussed, ecosystem participants should consider committing to a common standard, such that designs can be combined. At present, large-scale players in the industry are forming different consortiums and standards. A global and well-accepted standard is crucial to enabling the idea of the Lego principle.
Adoption of new development paradigms and openness. To ensure the successful adoption of chiplets, various participants along the value chain (intellectual property, foundry, integrated device manufacturers, and packaging) could pursue new models of collaboration. While this is seen as a critical element by all participants, it may be difficult to achieve in a timely manner. This is due, in part, to challenges with intellectual property and open questions regarding responsibilities, such as identifying which party will be responsible for the overall reliable operation of the chip, with various parties supplying its building blocks. From a validation and verification perspective, value chain participants see the mix-and-match “shop” approach to chiplet creation as unrealistic.
Expected timeline and rollout for chiplets
Most senior leaders in the value chain expect to see broader chiplet adoption within the next decade. In the survey, 48 percent of industry leaders expect chiplets for automotive applications to emerge between 2027 and 2030, while 38 percent predict between 2030 and 2035. Only 8 percent anticipate the technology will advance sooner, between 2025 and 2027. The delay is not surprising, given general ramp-up and development times in the automotive sector.
Furthermore, the transition to chiplets is expected to be gradual. While the Lego principle is compelling, the first chiplet designs will most likely be homogenous. In these designs, intellectual property blocks would come from the same vendor and use a proprietary or established standard such as the peripheral component interconnect express (PCIe). A design with building blocks from one external party will most likely be the next step, also facilitating questions of responsibility. Real heterogenous designs with true multivendor or multitechnology node-size combinations will most likely emerge in the mid-2030s and beyond.
The relevance of chiplet-based designs is clear because they allow chips to circumvent existing boundaries as compute demands increase, while staying cost efficient. Once the chiplet ecosystem and standards are realized, stakeholders should quantify the benefits and opportunities for the application scenario at hand.
Implications of fusion chips and chiplets for players across the automotive semiconductor value chain
The rise of SDVs and supply chain issues has spurred automotive OEMs to move deeper into the semiconductor value chain. OEMs recognize that a comprehensive understanding of semiconductor technology to enable state-of-the-art features in the autonomous driving and infotainment domain has become vital for staying competitive.
This trend has implications for all player archetypes in the automotive semiconductor landscape, particularly for OEMs, tier-one suppliers, IDMs, and fabless players. As previously discussed, the decision to adopt fusion chips will most likely need to be made within the next two to four years, while the question of implementing chiplets will likely be addressed further in the future.
Market developments driven by centralization and consolidation
The market for automotive compute units is expected to grow from $96 billion in 2023 to $148 billion in 2030, corresponding to a CAGR of 6 percent (Exhibit 4).
In particular, the trends of centralization and consolidation translate into limited growth of the body and chassis domains, at only 1 to 2 percent a year, or even a slight decline for powertrain units. These units may even see a decrease, given that their functionality will be implemented in zonal controllers or centralized compute units such as the vehicle motion compute unit. ADAS/AD and infotainment units show CAGRs of 22 percent and 6 percent, respectively. The former is driven by the increasing number of vehicles with L2+ and above functionality (such as hands-off, eyes-off, and conditional autonomous driving).
According to McKinsey analysis, it is estimated that zonal controllers will have a market value of $3 billion in 2030, with centralized compute units (such as fusion SoCs and vehicle motion compute units) accounting for $8 billion.
Implications for OEMs
OEMs should consider the following areas of strategic relevance when deciding whether or not to pursue fusion SoCs:
- Software know-how. Is there sufficient know-how and control over the software architecture in these two domains to cope with the integration needs?
- ADAS/AD. What level of autonomous driving should be supported, and what kind of functionality should be hosted on the fusion SoC?
- Governance. How are the infotainment and ADAS/AD groups set up? How feasible are aligned development and release timelines?
- Sourcing strategy. Would sourcing chips for ADAS/AD and infotainment from the same supplier impede any strategic sourcing decisions and supply chain resilience topics?
- BOM versus total cost of ownership economics. What share of costs could be saved on a BOM basis? What does the business case look like when taking a total cost of ownership perspective into account and considering the requirements in the first few years of investment (such as new development paradigms and new tooling)?
Regarding chiplets, three plays may be feasible. First, OEMs may simply rely on their IDMs and fabless partners to drive the chiplet evolution. Second, OEMs may engage actively by joining standardization bodies (for example, the UCIe) and ensure that specific requirements are incorporated. Third, OEMs could actively develop chiplets on their own; however, this option would require substantial resources, including building up dedicated, specialized teams.
Implications for tier-one suppliers
Tier-one suppliers may follow up on the fusion SoC trend by creating their own centralized compute unit designs leveraging fusion SoCs. They could use these designs to showcase potential technical and commercial benefits for OEMs. Several tier-one suppliers are pursuing this strategy to prepare for the upcoming start of production between 2026 and 2028.10
Tier-one suppliers have available a similar scope of chiplet options as do OEMs. Tier-one suppliers may want to engage with OEMs early to incorporate their needs regarding chiplets into development road maps for the next-generation centralized compute units.
Implications for foundries, IDMs, and fabless players
While the impact and rise of fusion chips will most likely have a limited effect on foundries, IDMs, and fabless players, the relevance of chiplets will raise broader questions of responsibility and “ownership” of the final manufactured chip. Technical topics aside, the following strategic areas may be most germane:
- Ecosystems. What are the winning ecosystems and standards? For which standards is it worthwhile to invest and participate early on?
- Intellectual property ownership. Who will hold the portfolio of intellectual property “Lego blocks” from which the final chip will be created?
- Responsibility. Who will be the responsible for the final functionality of the chip in case of an issue that appears only in the field? Additionally, will this party be responsible for manufacturing the chip and handling the interconnections, or will the party that has provided the intellectual property be responsible?
- Development. What additional tooling and methods are needed to facilitate multivendor chiplet ecosystems? How will design verification and validation processes need to change for chiplet-based systems?
- Business models.What do pricing and licensing schemes look like? Who gets compensated for what?
Semiconductors will play an ever-increasing role in centralized compute units in the future. As such, OEMs are moving deeper into the automotive semiconductor value chain and engaging more actively in the choice of components, features, and specifications. A robust understanding of fusion chips and chiplet-based design technology, their benefits and challenges, and potential considerations will allow stakeholders across the automotive semiconductor value chain to stay flexible and competitive in the next generation of software-driven vehicles.
